Talk by Ping-Chen Huang from UC Berkeley. Given to the Redwood Center for Theoretical Neuroscience at UC Berkeley.
The escalating statistical variation of device behaviors in the nano-scale era has led to a search for alternative computational paradigms where randomness and statistics can be treated as opportunities rather than nuisance. This will allow computational systems to be built with circuits designed at the nominal case and have better access to the advantages of scaled technologies. Such computational paradigms may emerge as we explore the information processing in the biological sensory systems, which achieve unparalleled performance and energy efficiency with mediocre and unreliable components. Implementations of signal processing tasks such as feature extraction, learning, or recognition can especially benefit from bio-inspired computational models. In this talk, we will present a bio-inspired artificial olfactory system, which consists of an analog feature extraction front end that operates efficiently in the low-precision regime and a spike pattern classifier that exploits the randomness and statistics in circuits.
The analog front end implements a novel trainable feature extraction algorithm for metal-oxide gas sensor arrays. The algorithm extracts one composite feature of all analytes and transforms the sensor responses into concentration-invariant spike patterns. This composite feature is extracted by performing the gradient decent algorithm during training. This 6-channel analog frond end consumes 519nW/channel in the training mode, and 463nW/channel in the recognition mode.
The spike pattern classifier consists of a sparse transformation of the input spikes and a cortical memory model. The transformation is based on a random sampling scheme that can be efficiently performed with circuits exhibiting large parametric variations. Moreover, sparse representations allow fast and robust pattern storage and retrieval with associative memories such as the correlation matrix memory. It’s realized today that hyper-dimensional computing architectures like this may be a perfect match to the emerging nano-scale devices. We will show how this classifier can be densely and efficiently implemented in a 3-D CNFET-RRAM technology.